[建模]The causes of these errors in CST MWS

Hi, everyone! F:*[  
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Here I have some problems of a PCB simulation. The job is to test the radiation of a clock circult of a FPGA chip. )Dk0V!%N  
1: I imported the model to CST MWS and defined 2 discrete ports at the start and the end of that circult respectively. 1jUhG2y  
2: I adjusted the mesh properties with the consideration of reducing the simulation time, and now the mesh number is in an acceptable quantity. jm#d7@~4  
3: The solver is FDTD and then some problems happened. $L<_uqSk  
I will attach a graph to explain the problem more clearly. Hope some guys could help me out with these problems or some tips are good enough:)!  t_dw}I  
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图片:591_67912_00d2588cd671a4c.jpg

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图片:591_67912_5ff2a7b8f098eb3.jpg

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[attachment=3403 .. *O(/UVuD\  
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So, what are the problems? #hE3~+i  
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PS: CST MWS transient solver uses FIT but not FDTD.

what·s the meaning you were trying to express？ what is your problem？

Im really really sorry. I forgot to mention the problems that day. o\[nGf C&  
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The problem is: After I launched the simulation, there happened a problem that: the discrete port 1 and 2 are in the perfect conducted metal plane (Im sorry I couldnt remember the exact description as now the CST is occupied by others, thus I can't run it again and attach the graph.)

I found it...Thanks for your patience, guys:)  oo2VT  
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图片:591_67912_d7a86bcddce1e13.jpg

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Modified your post to adjust the picture size. :R_(+EK1  
hefang K@hv[4  

Any chance to upload your model file? z6$W@-Vd  
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1. What are the purple and green solids' (substrates) material properties? Lylw('zZ  
2. What's the background material in your model?

mesh view, you will find that the center of the port have been changed.

I'd like to upload my model but unfortunately, it is seriously against the company rules, and I can't even take this file back home. That's why I can only ask you guys while im working and in English. $Qn&jI38  
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Anyway, I'll try to explain the model: This PCB is made of 12 layers, between each two, there is a substrate layer YYTO,4  
The material of 12 layers is LOSSY METAL, with 5.8e+007 S/m electric conductivity, Mue =1 "_nX5J9  
The material of the substrates is NORMAL; with Epsilon (relative dielectric constant )=4.3, Mue =1 XoDJzrL#  
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Hefang, you've asked me about the meaning of the purple and green solids, well, these represent the different layers. The purple one is the second layer, and I believe that both the port 1 and port 2 locate on the layer 1 (The metal micro strip in graph 2). As for the green one, it's hard to tell which layer it is because the similar colors of the adjacent layers that my colleagues used.

Depend on the snapshots without physically "see" the model, it's hard for me to locate the root cause. wtlB  
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What's the total thickness of the PCB, as well as the thickness of the copper and the substrate (the seperation of layers)? r~I.F!{  
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Or, as haihun suggested, active the mesh view and check the discrete port location. What is the global mesh properties? I noticed that you reduced the mesh numbers. Then it's a potential risk in low mesh density that the actual discrete port location in mesh view is NOT the same in modelling view. If the ports touch any of the coppers, then the error message is reasonable.