[其它]Digital.Logic.And.Microprocessor.Design.With.VHDL

Contents pxP7yJL`  
  @%RDw*L(  
Contents....................................................................................................................................................................  \&SP7~-eq  
Preface...................................................................................................................................................................  '*K/K],S]  
Chapter 1  Designing Microprocessors......................................................................................  '?#e$<uS-  
1.1 Overview of a Microprocessor.......................................................................................................................  JBuorc  
1.2 Design Abstraction Levels..............................................................................................................................  Xc'yz 2B  
1.3 Examples of a 2-to-1 Multiplexer...................................................................................................................  Qg3 -%i/@  
1.3.1 Behavioral Level....................................................................................................................................  $)kIYM&  
1.3.2 Gate Level..............................................................................................................................................  Hd4&"oeY  
1.3.3 Transistor Level.....................................................................................................................................  ]Dx5t&  
1.4 Introduction to VHDL....................................................................................................................................  K5!k06;s  
1.5 Synthesis.......................................................................................................................................................  i<-#yL5  
1.6 Going Forward..............................................................................................................................................  X\M0Q%8  
1.7 Summary Checklist.......................................................................................................................................  +W-sb5)  
1.8 Problems.......................................................................................................................................................  K2NnA  
Chapter 2  Digital Circuits..........................................................................................................2  zVp|%&  
2.1 Binary Numbers..............................................................................................................................................3  Ff|?<\x0}A  
2.2 Binary Switch.................................................................................................................................................  yfYAA*S!z  
2.3 Basic Logic Operators and Logic Expressions............................................................................................... D`Fl*Wc4H  
2.4 Truth Tables....................................................................................................................................................  <>p\9rVp*^  
2.5 Boolean Algebra and Boolean Function.........................................................................................................  (xq25;|Y  
2.5.1 Boolean Algebra....................................................................................................................................  o6'`W2P  
2.5.2 * Duality Principle...............................................................................................................................  bE0cW'6r  
2.5.3 Boolean Function and the Inverse........................................................................................................  tk~7>S  
2.6 Minterms and Maxterms...............................................................................................................................  y
BeSvsm  
2.6.1 Minterms..............................................................................................................................................  t:W`=^  
2.6.2 * Maxterms..........................................................................................................................................  F+9|D  
2.7 Canonical, Standard, and non-Standard Forms.............................................................................................  9erTb?@S  
2.8 Logic Gates and Circuit Diagrams................................................................................................................  ?"J5~_U
.  
2.9 Example: Designing a Car Security System.................................................................................................  >:8GU f*  
2.10 VHDL for Digital Circuits............................................................................................................................  e>X&[\T  
2.10.1 VHDL code for a 2-input NAND gate.................................................................................................  o)srE5  
2.10.2 VHDL code for a 3-input NOR gate....................................................................................................  k'EP->
r  
2.10.3 VHDL code for a function...................................................................................................................  Zn&X Uvdl  
2.11 Summary Checklist.......................................................................................................................................  0lY.z$V  
2.12 Problems.......................................................................................................................................................  !=Cd1 $<  
Chapter 3  Combinational Circuits............................................................................................  9qW^@5
m  
3.1 Analysis of Combinational Circuits................................................................................................................  k(!#^Mlz[  
3.1.1 Using a Truth Table...............................................................................................................................  <{:$]3  
3.1.2 Using a Boolean Function......................................................................................................................  ,C!MHn^$  
3.2 Synthesis of Combinational Circuits..............................................................................................................  A03,X;S+  
3.3 * Technology Mapping...................................................................................................................................  vxY7/_]  
3.4 Minimization of Combinational Circuits......................................................................................................  N(6|TE2  
3.4.1 Karnaugh Maps....................................................................................................................................  m8#+w0p)  
3.4.2 Don’t-cares..........................................................................................................................................  6imDA]5N&
 
3.4.3 * Tabulation Method............................................................................................................................  `G6Nk@9.  
3.5 * Timing Hazards and Glitches....................................................................................................................  r>A,7{  
3.5.1 Using Glitches.....................................................................................................................................  rWAJL9M  
3.6 BCD to 7-Segment Decoder.........................................................................................................................   pb6z)8  
3.7 VHDL for Combinational Circuits...............................................................................................................  e&#qj^  
3.7.1 Structural BCD to 7-Segment Decoder................................................................................................  PudwcP{  
3.7.2 Dataflow BCD to 7-Segment Decoder................................................................................................  }D{y u+)  
3.7.3 Behavioral BCD to 7-Segment Decoder..............................................................................................  LeXuTd  
3.8 Summary Checklist.......................................................................................................................................  L:j;;9Sp{  
3.9 Problems.......................................................................................................................................................  !/sXG\  
Chapter 4  Standard Combinational Components...................................................................  T^%$  
4.1 Signal Naming Conventions...........................................................................................................................  L-",.U*;  
4.2 Adder..............................................................................................................................................................  vaS/WEY  
4.2.1 Full Adder..............................................................................................................................................  _L<IxOZh+  
4.2.2 Ripple-carry Adder................................................................................................................................  `pOiv&>  
4.2.3 * Carry-lookahead Adder.......................................................................................................................  `gSqwN<x%  
4.3 Two’s Complement Binary Numbers.............................................................................................................  c5nl!0XX  
4.4 Subtractor........................................................................................................................................................  ;WWUxrWif  
4.5 Adder-Subtractor Combination.....................................................................................................................  ~;9B\fE`  
4.6 Arithmetic Logic Unit...................................................................................................................................  1s"6  
4.7 Decoder.........................................................................................................................................................  5$`ihO?  
4.8 Encoder.........................................................................................................................................................  rq:R6e  
4.8.1 * Priority Encoder................................................................................................................................  ]|@RWzA  
4.9 Multiplexer...................................................................................................................................................  ;gP@d`s  
4.9.1 * Using Multiplexers to Implement a Function...................................................................................  R^{O
w  
4.10 Tri-state Buffer.............................................................................................................................................  uR"(0_  
4.11 Comparator...................................................................................................................................................  v=RQ"iv8  
4.12 Shifter...........................................................................................................................................................  ,=.&  
4.12.1 * Barrel Shifter....................................................................................................................................  zkA"2dh  
4.13 * Multiplier...................................................................................................................................................  m?`U;R[  
4.14 Summary Checklist.......................................................................................................................................  wspZ Eu>C;  
4.15 Problems.......................................................................................................................................................  2*ZB[5_V  
Chapter 5 * Implementation Technologies.............................................................................  LSs!U 3"  
5.1 Physical Abstraction.......................................................................................................................................  2<y!3OeN  
5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)..................................................................  YP5V~-O/  
5.3 CMOS Logic...................................................................................................................................................  +W x
/zo  
5.4 CMOS Circuits...............................................................................................................................................  eZ8~t/8  
5.4.1 CMOS Inverter......................................................................................................................................  !:'%'@uc  
5.4.2 CMOS NAND gate................................................................................................................................ 
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5.4.3 CMOS AND gate...................................................................................................................................  OjcxD5"v9  
5.4.4 CMOS NOR and OR Gates................................................................................................................ 1  t6W$t  
5.4.5 Transmission Gate...............................................................................................................................  ckHHD|  
5.4.6 2-input Multiplexer CMOS Circuit..................................................................................................... 1  6p=AzojoB  
5.4.7 CMOS XOR and XNOR Gates............................................................................................................ 1  YQ:FBj  
5.5 Analysis of CMOS Circuits......................................................................................................................... .1  8F9sKRq|rO  
5.6 Using ROMs to Implement a Function........................................................................................................ .15  n3da@ClBt  
5.7 Using PLAs to Implement a Function.......................................................................................................... 1  9|jk=`4UK  
5.8 Using PALs to Implement a Function.......................................................................................................... 1  6av]LYK  
5.9 Complex Programmable Logic Device (CPLD)...........................................................................................  NnRR"'  
5.10 Field Programmable Gate Array (FPGA).....................................................................................................  rd vq(\A  
5.11 Summary Checklist.......................................................................................................................................  f,wB.MN  
5.12 Problems.......................................................................................................................................................  b%z4u0  
Chapter 6  Latches and Flip-Flops............................................................................................  -U`]/  
6.1 Bistable Element.............................................................................................................................................  tg_v\n  
6.2 SR Latch.........................................................................................................................................................  WyF1Fw  
6.3 SR Latch with Enable.....................................................................................................................................  0B7cpw>_J  
6.4 D Latch...........................................................................................................................................................  .BuXg<`  
6.5 D Latch with Enable.......................................................................................................................................  A(S=  
6.6 Clock...............................................................................................................................................................  7Y"CeU-S  
6.7 D Flip-Flop.................................................................................................................................................. .1  URz$hcI8  
6.7.1 * Alternative Smaller Circuit............................................................................................................... 1  }\!&3^I  
6.8 D Flip-Flop with Enable............................................................................................................................... 1  xlg6cO  
6.9 Asynchronous Inputs.................................................................................................................................... 1  y9kydu#q  
6.10 Description of a Flip-Flop............................................................................................................................  ;-Fr^|do y  
6.10.1 Characteristic Table............................................................................................................................. 1  tXDO@YH3S  
6.10.2 Characteristic Equation........................................................................................................................ 1  #+I)<a7\  
6.10.3 State Diagram...................................................................................................................................... 1  G$kspN*"A  
6.10.4 Excitation Table................................................................................................................................... 1  o&g-0!"  
6.11 Timing Issues................................................................................................................................................ 1  kGR5!8$z  
6.12 Example: Car Security System – Version 2..................................................................................................  E`]lr[  
6.13 VHDL for Latches and Flip-Flops................................................................................................................ 1  +n_`*@SE  
6.13.1 Implied Memory Element.................................................................................................................... 1  ?0QoYA@.$  
6.13.2 VHDL Code for a D Latch with Enable..............................................................................................  U{6i5;F#H  
6.13.3 VHDL Code for a D Flip-Flop........................................................................................................... .19  )GhMM  
6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear...................................  ^LO=&Cq  
6.14 * Flip-Flop Types.........................................................................................................................................  F0 x5(lpQ  
6.14.1 SR Flip-Flop........................................................................................................................................  _1TSt%L  
6.14.2 JK Flip-Flop.........................................................................................................................................  #z$FxZT<b  
6.14.3 T Flip-Flop...........................................................................................................................................  u2%/</]h  
6.15 Summary Checklist.......................................................................................................................................  zX*+J"x  
6.16 Problems.......................................................................................................................................................  Lx6C fR  
Chapter 7  Sequential Circuits...................................................................................................2  a7KP_[_(  
7.1 Finite-State-Machine (FSM) Models..............................................................................................................  XMzL\Edo
 
7.2 State Diagrams................................................................................................................................................  mMo<C_~w&  
7.3 Analysis of Sequential Circuits.......................................................................................................................  cK6M8:KW  
7.3.1 Excitation Equation...............................................................................................................................  Pp.qDkT  
7.3.2 Next-state Equation...............................................................................................................................  tu{y  
7.3.3 Next-state Table.....................................................................................................................................  b~uz\%'3  
7.3.4 Output Equation...................................................................................................................................  f-!t31?XK  
7.3.5 Output Table............................................................................... .. j{PuZ^v1  
[+dOgyK  

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Digital.Logic.And.Microprocessor.Design.With.VHDL.[bbs.rfeda.cn].part2.rar

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thanks a lot

谢谢分享 $T*kpUXH}  
  

谢谢，不错。

好东西

精神可嘉！！！

最近因工作需要，正需要看vhdl方面的书，多谢楼主分享