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[其它]Digital.Logic.And.Microprocessor.Design.With.VHDL

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0楼发表于: 2008-11-17 10:49:33

Contents

Contents....................................................................................................................................................................
Preface...................................................................................................................................................................
Chapter 1 Designing Microprocessors......................................................................................
1.1 Overview of a Microprocessor.......................................................................................................................
1.2 Design Abstraction Levels..............................................................................................................................
1.3 Examples of a 2-to-1 Multiplexer...................................................................................................................
1.3.1 Behavioral Level....................................................................................................................................
1.3.2 Gate Level..............................................................................................................................................
1.3.3 Transistor Level.....................................................................................................................................
1.4 Introduction to VHDL....................................................................................................................................
1.5 Synthesis.......................................................................................................................................................
1.6 Going Forward..............................................................................................................................................
1.7 Summary Checklist.......................................................................................................................................
1.8 Problems.......................................................................................................................................................
Chapter 2 Digital Circuits..........................................................................................................2
2.1 Binary Numbers..............................................................................................................................................3
2.2 Binary Switch.................................................................................................................................................
2.3 Basic Logic Operators and Logic Expressions...............................................................................................
2.4 Truth Tables....................................................................................................................................................
2.5 Boolean Algebra and Boolean Function.........................................................................................................
2.5.1 Boolean Algebra....................................................................................................................................
2.5.2 * Duality Principle...............................................................................................................................
2.5.3 Boolean Function and the Inverse........................................................................................................
2.6 Minterms and Maxterms...............................................................................................................................
2.6.1 Minterms..............................................................................................................................................
2.6.2 * Maxterms..........................................................................................................................................
2.7 Canonical, Standard, and non-Standard Forms.............................................................................................
2.8 Logic Gates and Circuit Diagrams................................................................................................................
2.9 Example: Designing a Car Security System.................................................................................................
2.10 VHDL for Digital Circuits............................................................................................................................
2.10.1 VHDL code for a 2-input NAND gate.................................................................................................
2.10.2 VHDL code for a 3-input NOR gate....................................................................................................
2.10.3 VHDL code for a function...................................................................................................................
2.11 Summary Checklist.......................................................................................................................................
2.12 Problems.......................................................................................................................................................
Chapter 3 Combinational Circuits............................................................................................
3.1 Analysis of Combinational Circuits................................................................................................................
3.1.1 Using a Truth Table...............................................................................................................................
3.1.2 Using a Boolean Function......................................................................................................................
3.2 Synthesis of Combinational Circuits..............................................................................................................
3.3 * Technology Mapping...................................................................................................................................
3.4 Minimization of Combinational Circuits......................................................................................................
3.4.1 Karnaugh Maps....................................................................................................................................
3.4.2 Don’t-cares..........................................................................................................................................
3.4.3 * Tabulation Method............................................................................................................................
3.5 * Timing Hazards and Glitches....................................................................................................................
3.5.1 Using Glitches.....................................................................................................................................
3.6 BCD to 7-Segment Decoder.........................................................................................................................
3.7 VHDL for Combinational Circuits...............................................................................................................
3.7.1 Structural BCD to 7-Segment Decoder................................................................................................
3.7.2 Dataflow BCD to 7-Segment Decoder................................................................................................
3.7.3 Behavioral BCD to 7-Segment Decoder..............................................................................................
3.8 Summary Checklist.......................................................................................................................................
3.9 Problems.......................................................................................................................................................
Chapter 4 Standard Combinational Components...................................................................
4.1 Signal Naming Conventions...........................................................................................................................
4.2 Adder..............................................................................................................................................................
4.2.1 Full Adder..............................................................................................................................................
4.2.2 Ripple-carry Adder................................................................................................................................
4.2.3 * Carry-lookahead Adder.......................................................................................................................
4.3 Two’s Complement Binary Numbers.............................................................................................................
4.4 Subtractor........................................................................................................................................................
4.5 Adder-Subtractor Combination.....................................................................................................................
4.6 Arithmetic Logic Unit...................................................................................................................................
4.7 Decoder.........................................................................................................................................................
4.8 Encoder.........................................................................................................................................................
4.8.1 * Priority Encoder................................................................................................................................
4.9 Multiplexer...................................................................................................................................................
4.9.1 * Using Multiplexers to Implement a Function...................................................................................
4.10 Tri-state Buffer.............................................................................................................................................
4.11 Comparator...................................................................................................................................................
4.12 Shifter...........................................................................................................................................................
4.12.1 * Barrel Shifter....................................................................................................................................
4.13 * Multiplier...................................................................................................................................................
4.14 Summary Checklist.......................................................................................................................................
4.15 Problems.......................................................................................................................................................
Chapter 5 * Implementation Technologies.............................................................................
5.1 Physical Abstraction.......................................................................................................................................
5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)..................................................................
5.3 CMOS Logic...................................................................................................................................................
5.4 CMOS Circuits...............................................................................................................................................
5.4.1 CMOS Inverter......................................................................................................................................
5.4.2 CMOS NAND gate................................................................................................................................
5.4.3 CMOS AND gate...................................................................................................................................
5.4.4 CMOS NOR and OR Gates................................................................................................................ 1
5.4.5 Transmission Gate...............................................................................................................................
5.4.6 2-input Multiplexer CMOS Circuit..................................................................................................... 1
5.4.7 CMOS XOR and XNOR Gates............................................................................................................ 1
5.5 Analysis of CMOS Circuits......................................................................................................................... .1
5.6 Using ROMs to Implement a Function........................................................................................................ .15
5.7 Using PLAs to Implement a Function.......................................................................................................... 1
5.8 Using PALs to Implement a Function.......................................................................................................... 1
5.9 Complex Programmable Logic Device (CPLD)...........................................................................................
5.10 Field Programmable Gate Array (FPGA).....................................................................................................
5.11 Summary Checklist.......................................................................................................................................
5.12 Problems.......................................................................................................................................................
Chapter 6 Latches and Flip-Flops............................................................................................
6.1 Bistable Element.............................................................................................................................................
6.2 SR Latch.........................................................................................................................................................
6.3 SR Latch with Enable.....................................................................................................................................
6.4 D Latch...........................................................................................................................................................
6.5 D Latch with Enable.......................................................................................................................................
6.6 Clock...............................................................................................................................................................
6.7 D Flip-Flop.................................................................................................................................................. .1
6.7.1 * Alternative Smaller Circuit............................................................................................................... 1
6.8 D Flip-Flop with Enable............................................................................................................................... 1
6.9 Asynchronous Inputs.................................................................................................................................... 1
6.10 Description of a Flip-Flop............................................................................................................................
6.10.1 Characteristic Table............................................................................................................................. 1
6.10.2 Characteristic Equation........................................................................................................................ 1
6.10.3 State Diagram...................................................................................................................................... 1
6.10.4 Excitation Table................................................................................................................................... 1
6.11 Timing Issues................................................................................................................................................ 1
6.12 Example: Car Security System – Version 2..................................................................................................
6.13 VHDL for Latches and Flip-Flops................................................................................................................ 1
6.13.1 Implied Memory Element.................................................................................................................... 1
6.13.2 VHDL Code for a D Latch with Enable..............................................................................................
6.13.3 VHDL Code for a D Flip-Flop........................................................................................................... .19
6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear...................................
6.14 * Flip-Flop Types.........................................................................................................................................
6.14.1 SR Flip-Flop........................................................................................................................................
6.14.2 JK Flip-Flop.........................................................................................................................................
6.14.3 T Flip-Flop...........................................................................................................................................
6.15 Summary Checklist.......................................................................................................................................
6.16 Problems.......................................................................................................................................................
Chapter 7 Sequential Circuits...................................................................................................2
7.1 Finite-State-Machine (FSM) Models..............................................................................................................
7.2 State Diagrams................................................................................................................................................
7.3 Analysis of Sequential Circuits.......................................................................................................................
7.3.1 Excitation Equation...............................................................................................................................
7.3.2 Next-state Equation...............................................................................................................................
7.3.3 Next-state Table.....................................................................................................................................
7.3.4 Output Equation...................................................................................................................................
7.3.5 Output Table............................................................................... ..

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