[其它]Digital.Logic.And.Microprocessor.Design.With.VHDL

Contents `FB?cPR  
  v9`B.(Ru  
Contents....................................................................................................................................................................  K2MNaB  
Preface...................................................................................................................................................................  tKsM}+fq  
Chapter 1  Designing Microprocessors......................................................................................  W#\};
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1.1 Overview of a Microprocessor.......................................................................................................................  "XsY~  
1.2 Design Abstraction Levels..............................................................................................................................  N3c)ce7[  
1.3 Examples of a 2-to-1 Multiplexer...................................................................................................................  NEou2y+}  
1.3.1 Behavioral Level....................................................................................................................................  "/Q(UV<d  
1.3.2 Gate Level..............................................................................................................................................  L
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1.3.3 Transistor Level.....................................................................................................................................  !
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1.4 Introduction to VHDL....................................................................................................................................  fQ_8{=<-&X  
1.5 Synthesis.......................................................................................................................................................  GhQ`{iJM  
1.6 Going Forward..............................................................................................................................................  X6*y/KGN  
1.7 Summary Checklist.......................................................................................................................................  `&[:!U2]F  
1.8 Problems.......................................................................................................................................................  uvv-lAbjw  
Chapter 2  Digital Circuits..........................................................................................................2  UVmyOC[Y{  
2.1 Binary Numbers..............................................................................................................................................3  _v=WjN  
2.2 Binary Switch.................................................................................................................................................  [K@!JY  
2.3 Basic Logic Operators and Logic Expressions............................................................................................... L=
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2.4 Truth Tables....................................................................................................................................................  A'-YwbY  
2.5 Boolean Algebra and Boolean Function.........................................................................................................  'yRv~BA  
2.5.1 Boolean Algebra....................................................................................................................................  d*(Bs$De  
2.5.2 * Duality Principle...............................................................................................................................  $<% nt  
2.5.3 Boolean Function and the Inverse........................................................................................................  zp-~'
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2.6 Minterms and Maxterms...............................................................................................................................  0Ilvr]1a4  
2.6.1 Minterms..............................................................................................................................................  !,!tNs1 K  
2.6.2 * Maxterms..........................................................................................................................................  LF.~rmPa  
2.7 Canonical, Standard, and non-Standard Forms.............................................................................................  >P"/nS"nn  
2.8 Logic Gates and Circuit Diagrams................................................................................................................  n]c,0N  
2.9 Example: Designing a Car Security System.................................................................................................  gL"Q.ybA  
2.10 VHDL for Digital Circuits............................................................................................................................  :BxYaAVt^  
2.10.1 VHDL code for a 2-input NAND gate.................................................................................................  bK%tQeT  
2.10.2 VHDL code for a 3-input NOR gate....................................................................................................  |/\1nWD  
2.10.3 VHDL code for a function...................................................................................................................  '?GZ"C2  
2.11 Summary Checklist.......................................................................................................................................  PlRs-%d  
2.12 Problems.......................................................................................................................................................  =d.W'q|  
Chapter 3  Combinational Circuits............................................................................................  @wJa33QT  
3.1 Analysis of Combinational Circuits................................................................................................................  XXmu|h  
3.1.1 Using a Truth Table...............................................................................................................................  V*uu:  
3.1.2 Using a Boolean Function......................................................................................................................  {&qsh9ob  
3.2 Synthesis of Combinational Circuits..............................................................................................................  !r
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3.3 * Technology Mapping...................................................................................................................................  }(}vlL  
3.4 Minimization of Combinational Circuits......................................................................................................  -+@~*$ d  
3.4.1 Karnaugh Maps....................................................................................................................................  y/VmjsN}  
3.4.2 Don’t-cares..........................................................................................................................................  ibUPd."W  
3.4.3 * Tabulation Method............................................................................................................................  ]!o,S{a&  
3.5 * Timing Hazards and Glitches....................................................................................................................  R*eM 1  
3.5.1 Using Glitches.....................................................................................................................................  bJ!f,a'/  
3.6 BCD to 7-Segment Decoder.........................................................................................................................  0 3 $ W  
3.7 VHDL for Combinational Circuits...............................................................................................................  >.~k?_Of  
3.7.1 Structural BCD to 7-Segment Decoder................................................................................................  8>;o MM  
3.7.2 Dataflow BCD to 7-Segment Decoder................................................................................................  c}s3c >`d  
3.7.3 Behavioral BCD to 7-Segment Decoder..............................................................................................  ^@"f%3  
3.8 Summary Checklist.......................................................................................................................................  sswAI|6ou  
3.9 Problems.......................................................................................................................................................  o;I86dI6C  
Chapter 4  Standard Combinational Components...................................................................  g c=|<(  
4.1 Signal Naming Conventions...........................................................................................................................  RW8u0 ?b  
4.2 Adder..............................................................................................................................................................  =H
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4.2.1 Full Adder..............................................................................................................................................  =DwH*U/YR  
4.2.2 Ripple-carry Adder................................................................................................................................  ~2ei+#d!^  
4.2.3 * Carry-lookahead Adder.......................................................................................................................  yE{UV>ry  
4.3 Two’s Complement Binary Numbers.............................................................................................................  xl=|]8w  
4.4 Subtractor........................................................................................................................................................  481u1  
4.5 Adder-Subtractor Combination.....................................................................................................................  IQY#EyTb  
4.6 Arithmetic Logic Unit...................................................................................................................................  Gfch|Q^INy  
4.7 Decoder.........................................................................................................................................................  7
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4.8 Encoder.........................................................................................................................................................  )@M|YM1+  
4.8.1 * Priority Encoder................................................................................................................................  K%_JQ0`  
4.9 Multiplexer...................................................................................................................................................  n:z>l,`C]  
4.9.1 * Using Multiplexers to Implement a Function...................................................................................  !gQ(1u|r  
4.10 Tri-state Buffer.............................................................................................................................................  WTN!2b  
4.11 Comparator...................................................................................................................................................  MRu+:Y=K  
4.12 Shifter...........................................................................................................................................................  cu|q&  
4.12.1 * Barrel Shifter....................................................................................................................................  s7LX  
4.13 * Multiplier...................................................................................................................................................  o:ob1G[p%  
4.14 Summary Checklist.......................................................................................................................................  HXo'^^}q;  
4.15 Problems.......................................................................................................................................................  .AS,]*?Zn%  
Chapter 5 * Implementation Technologies.............................................................................  )A;<'{t #L  
5.1 Physical Abstraction.......................................................................................................................................  24l9/v'  
5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)..................................................................  Yy1Pipv  
5.3 CMOS Logic...................................................................................................................................................  \?}.+v  
5.4 CMOS Circuits...............................................................................................................................................  `XY[HK  
5.4.1 CMOS Inverter......................................................................................................................................  3qZ{yr2N[  
5.4.2 CMOS NAND gate................................................................................................................................  |REU7?B  
5.4.3 CMOS AND gate...................................................................................................................................  'iK*#b8l  
5.4.4 CMOS NOR and OR Gates................................................................................................................ 1  EatDT*!  
5.4.5 Transmission Gate...............................................................................................................................  5@5="lNjS  
5.4.6 2-input Multiplexer CMOS Circuit..................................................................................................... 1  ZH:X4!  
5.4.7 CMOS XOR and XNOR Gates............................................................................................................ 1  UkQocZdZ  
5.5 Analysis of CMOS Circuits......................................................................................................................... .1  Id1[}B-T  
5.6 Using ROMs to Implement a Function........................................................................................................ .15  #}?$mxME*  
5.7 Using PLAs to Implement a Function.......................................................................................................... 1  tJ3s#q6  
5.8 Using PALs to Implement a Function.......................................................................................................... 1  dq&d>f1  
5.9 Complex Programmable Logic Device (CPLD)...........................................................................................  [r'M_foga*  
5.10 Field Programmable Gate Array (FPGA).....................................................................................................  V4D&&0&n  
5.11 Summary Checklist.......................................................................................................................................  vS
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5.12 Problems.......................................................................................................................................................  9rz"@LM  
Chapter 6  Latches and Flip-Flops............................................................................................  b2H6}s"=w  
6.1 Bistable Element.............................................................................................................................................  ](pD<FfS]'  
6.2 SR Latch.........................................................................................................................................................  bN)?szh&Y  
6.3 SR Latch with Enable.....................................................................................................................................  oQO3:2
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6.4 D Latch...........................................................................................................................................................  beoMLHp  
6.5 D Latch with Enable.......................................................................................................................................  6 h):o  
6.6 Clock...............................................................................................................................................................  Rwk|

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6.7 D Flip-Flop.................................................................................................................................................. .1  H*IoJL6
 
6.7.1 * Alternative Smaller Circuit............................................................................................................... 1  *z~Y*Q0  
6.8 D Flip-Flop with Enable............................................................................................................................... 1  ~XRr }z_Lq  
6.9 Asynchronous Inputs.................................................................................................................................... 1  DJ.C
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6.10 Description of a Flip-Flop............................................................................................................................  z=sqO'~  
6.10.1 Characteristic Table............................................................................................................................. 1  *V}}3Degh  
6.10.2 Characteristic Equation........................................................................................................................ 1  Lb/_ULo6-V  
6.10.3 State Diagram...................................................................................................................................... 1  ),eiJblH  
6.10.4 Excitation Table................................................................................................................................... 1  ]]4E)j8  
6.11 Timing Issues................................................................................................................................................ 1  +tF,E^  
6.12 Example: Car Security System – Version 2..................................................................................................  {iv=KF_S_  
6.13 VHDL for Latches and Flip-Flops................................................................................................................ 1  gg9W7%t/  
6.13.1 Implied Memory Element.................................................................................................................... 1  K||85l?<  
6.13.2 VHDL Code for a D Latch with Enable..............................................................................................  l=yO]a\QZ  
6.13.3 VHDL Code for a D Flip-Flop........................................................................................................... .19   %JZIg!  
6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear...................................  HT'dft #  
6.14 * Flip-Flop Types.........................................................................................................................................  #S5vX<"9  
6.14.1 SR Flip-Flop........................................................................................................................................  <LE>WfmC  
6.14.2 JK Flip-Flop.........................................................................................................................................  vL7}0n>tz  
6.14.3 T Flip-Flop...........................................................................................................................................  }m?L/Y'}  
6.15 Summary Checklist.......................................................................................................................................  w_  m  
6.16 Problems.......................................................................................................................................................  ?/~1z*XUW  
Chapter 7  Sequential Circuits...................................................................................................2  2#^[`sFPO  
7.1 Finite-State-Machine (FSM) Models..............................................................................................................  RK0IkRXQd  
7.2 State Diagrams................................................................................................................................................  V/Tp&+Z.c  
7.3 Analysis of Sequential Circuits.......................................................................................................................  C-7.Sa  
7.3.1 Excitation Equation...............................................................................................................................  sC j3h  
7.3.2 Next-state Equation...............................................................................................................................  j:
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7.3.3 Next-state Table.....................................................................................................................................  -3Ffk:  
7.3.4 Output Equation...................................................................................................................................  Xo,BuK&G  
7.3.5 Output Table............................................................................... .. s`{O-  
V}*b^<2o5  

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Digital.Logic.And.Microprocessor.Design.With.VHDL.[bbs.rfeda.cn].part2.rar

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thanks a lot

谢谢分享 -W>zO
N|l  
  

谢谢，不错。

好东西

精神可嘉！！！

最近因工作需要，正需要看vhdl方面的书，多谢楼主分享