[EMC]An EMC Design Risk Assessment Technique:None To Retest or Not to Retest?

Abstract: A technique is presented that provides for a o5*74Mv  
qualitative and quantitative assessment of the risk of failing @mQ/WYs  
to achieve EMC compliance when making minor hardware Zi<Sw  
design changes (component or PCB layout) on a product !~|"LA!jn  
that has already had a successhl compliance test performed. w{YtTZp3  
The EMC Design Risk Assessment (EDRA) technique uses evndw>  
a simple summation of risk scheme to allow design changes yO$r'9?,*  
to be gauged and the requirement for re-testing to be implied dFI.`pB  
from the total risk value. The technique allows a product -tK;RQYax  
supplier to make a quantified technical assessment of the ${TB2q}%  
impact of design changes on the compliance status and 8M3p\}O  
hence decide if a retest is required or can be avoided. The eSvc/CU
 
supplier may make the decision to not implement all of the C$2o o@   
suggested design changes in order to avoid retest costs an .. <M=W)2D7  
EvH(Po h  

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